Description: Position: PCIe Validation Engineer Experience: 5 8 Years Location : San Jose , ... , Lab Tools Role Highlights: PCIe subsystem validation on SoC platformsPost-silicon bring ...
2 days ago
... high-speed interfaces such as PCIe Gen5/Gen6 and LPDDR5. Responsibilities ... , PCB layout, board bring-up, validation, debugging, and end-to-en
2 days ago