Description: Title: Verification Engineer Location: San Jose, CA (5 days ... Design Functional Verification (SV/UVM) Software (Test) and Hardware (Emulation) ValidationWhat we ... -least 2+ years of experience in emulation (Cadence Palldium, Synopys HAPS) At ...
11 days ago
Description: Title: Verification Engineer Location: Sunnyvale, CA Type: Contract ... : The main function of the Verification Engineer is to work with a group ... researchers and engineers to own the electrical system level verification of client ...
27 days ago
Description: Title: Post Silicon Engineer Location: Sunnyvale, CA Type: Contract ... s/DSP) in Pre-Silicon (Virtual, Emulation and fpga platforms) & Post-Silicon ...
14 days ago