... seeking a Low Power Principal Engineer/ASIC Engineer to join our team in ... and verification (UPF, VCLP) - Power analysis and optimization (PTPX) - STA and ... timing analysis - Synthesis and physical design (DC ...
a day ago
... : Pre-Layout Synthesis and STA Engineer Key Responsibilities: 1. Perform pre-layout ... , and timing. 2. Conduct static timing analysis (STA) to ensure design meets ...
2 days ago