Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
2 days ago
... a highly skilled and motivated DFT Engineer with 6+ years of experience to ... will work closely with design, verification, and product engineering teams to ...
7 days ago
Description: Job Title: DFT Engineer (6+ Years) Location: Santa Clara, California, ... a highly skilled and motivated DFT Engineer with 6+ years of experience to ... will work closely with design, verification, and product engineering teams to ...
8 days ago