Description: Title: Analog Layout Engineer Work location: Pasadena, CA (Hybrid- ... without benefits Description As an Analog Layout Engineer, you will be responsible ... including resistors, capacitors and inductors.Design verification including DRC, LVS, ERC ...
3 days ago
Description: W2 Only Job Title: Senior CPU Performance Engineer Location: Santa Clara. CA ... are looking for a CPU performance engineer, who will participate in research ...
24 days ago