... Description: Job Title: Chip-Level Timing Constraint Development EngineerLocation: San Jose, ... and validate timing constraints (SDC) for complex chip-level ASIC designs Perform ... static timing analysis (STA) to ensure full timing ...
21 hours ago
... : Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term ... understanding of RTL synthesis, Static Timing Analysis & LEC Flows.Exp
5 hours ago