Description: Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) ... level verification Develop functional tests based on verification test plan Drive Design ... on defined verification metrics on test plan, functional and code coverage ...
28 days ago
... UVM, System Verilog, SVA Develop test plans and coverage metrics from ... write block and chip-level tests in C,SV,UVM Debug RTL ... simulations and work with design engineers to verify fixes. Write diagnostics ...
4 days ago
... .Understand design specs and develop test plans based on functional and ...
7 days ago
Description: Role: Design Verification Engineer Location: Mountain View, CA (Hybrid) ... : Contract Job Description Design Verification Engineer Key Responsibilities: 08-14 Years ... . Understand design specs and develop test plans based on functional and ...
12 days ago
... : Systems Hardware Architect / Design Verification Engineer Mountain View, CA NO 14 ... .Understand design specs and develop test plans based on functional and ...
14 days ago