... UVM, System Verilog, SVA Develop test plans and coverage metrics from ... and write block and chip-level tests in C,SV,UVM Debug RTL ... simulations and work with design engineers to verify fixes. Write diagnostics ...
26 days ago
... cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard ... integration in test bench, stress/corner testing, failure debug, gate level simulations ...
9 days ago
... .Understand design specs and develop test plans based on functional and ... environments for IP/subsystem/SoC level testingDevelop directed and random testcases ...
29 days ago
... an experienced Senior Design Verification Engineer to join our team, supporting ... , CA, with a focus on chip-level verification. Job Summary: We're ... Engineer with expertise in verifying complex digital designs at the chip level ...
20 days ago