Description: Role: Design Verification Engineer Location: Mountain View, CA (Hybrid) ... Type: Contract Job Description Design Verification Engineer Key Responsibilities: 08-14 Years ... Build UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
13 days ago
... : Architect block and full-chip verification environments using HVLs and constrained ... simulations and work with design engineers to verify fixes. Write diagnostics ...
5 days ago
... requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
8 days ago