... Responsibilities:Define and implement IP/SoC verification plans, build verification test ... to enable IP/sub-system/SoC level verification. Develop functional tests ...
18 days ago
... EngineerLocation: Sunnyvale, CA [On-site] SoC/DDR High speed design Interfaces ... ) independently. They have expertise in SoC/DDR design, memory devices, high ...
2 days ago
... validation of complex ASIC SOC and FPGA SOC - Perform Post-Silicon/FPGA ...
27 days ago
Description: Role: CAD/EDA Engineer Silicon Design/Verification Infrastructure Location: ... of experience in EDA/CAD SoC/IP design and/or verification ... work experience. Knowledge of ASIC/SoC design flows, SystemVerilog, and UVM ...
17 days ago
Description: Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) ... ) Responsibilities: Define and implement IP/SoC verification plans, build verification test ... to enable IP/sub-system/SoC level verification Develop functional tests ...
19 days ago
... ) independently. They have expertise in SoC/DDR design, memory devices, high ...
5 days ago
... verification environments at IP and SoC-level. Lead and manage verification ...
17 days ago
... information security field (e.g., network security, SOC analyst, endpoint management, vulnerability management ...
26 days ago
Description: Senior Design Verification Engineer SV/UVM Contract Long Term ... environments for IP, subsystem, and SoC-level simulationsWrite directed and constrained ...
2 days ago
Description: Position Title: Design Verification Engineer Location: Mountain View, CA - Onsite ... verification environments for IP/subsystem/SoC level testing Develop directed and ...
3 days ago
... : Systems Hardware Architect / Design Verification Engineer Mountain View, CA NO 14 ... verification environments for IP/subsystem/SoC level testingDevelop directed and random ...
5 days ago
... on mobile SoC from qualcomm, mediatek etc. Experienced Electrical Engineer to work ...
5 days ago
Description: Role: Hardware Validation Engineer Hiring Mode: Contract (TP) Location: ... ) independently. They have expertise in SoC/DDR design, memory devices, high ...
5 days ago
Description: Role: Silicon Validation Engineer Location: Mountain View, CA Duration: ... validation test plans for various SoC features and subsystems in one ...
6 days ago
... main function of Silicon Validation Engineer is to run, triage, and ... validation test plans for various SoC features and subsystems in one ...
11 days ago
Description: Job Title: PCIe Engineer (Peripheral Component Interconnect Express) Location: ... verification environments at IP and SoC-level. Lead and manage verification ...
12 days ago
Description: Job Title: PCIe Engineer (Peripheral Component Interconnect Express) Location: ... verification environments at IP and SoC-level. Lead and manage verification ...
16 days ago
Description: Role: Post-Silicon Validation Engineer Location: San Jose, CA Hybrid ... Engineering preferred. Strong background in SOC/VLSI/Mixed Signal IC bring ...
17 days ago
Description: Position Cybersecurity Engineer Location Toronto, Canada Position Type: ... : We are looking for a Cybersecurity Engineer with experience in OT environments ... in risk assessment (not just SOC monitoring). Strong knowledge of OT ...
4 days ago
Description: Role: Electrical Design Engineer Location: Sunnyvale, CA [On-site] ... Note: We need Engineers with Electrical/Electronic HW design ... ) independently. They have expertise in SoC/DDR design, memory devices, high ...
4 days ago