Description: Role: Design Verification Engineer Location: Mountain View, CA ( ... Contract Job Description Design Verification Engineer Key Responsibilities: 08-14 Years ... and architectural requirements Build UVM/System Verilog-based verification environments ...
23 hours ago
... looking for an Design Verification Engineer. Position type: Contract Duration: 12 ... (Onsite Job) As a Design Verification Engineer, you will need: Minimum Qualifications ... of AMBA protocols.Build UVM/System Verilog-based verification environments for ...
a day ago
Description: Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) ... benches to enable IP/sub-system/SoC level verification Develop functional ...
16 days ago
Description: Systems Hardware Architect / Design Verification Engineer Mountain View, CA NO 14+ ... functional and architectural requirementsBuild UVM/System Verilog-based verification environments for ...
2 days ago