... circuits - Signal integrity (SI) & power integrity (PI) - Bump, RDL, package ... and power/grid layout creation Key Responsibilities ... Collaborate with Signal Integrity and Power Integrity (SIPI) teams to ... and optimize signal and power int

23 days ago

High-Speed I/O Circuit Design Engineer

Dexian DISYS
Folsom

$71 $72 an hour

... -level simulations Signal Integrity (SI) & Power Integrity (PI) Bump, RDL, package ... , and power/grid layout creation Key Responsibilities ...

21 days ago

Silicon Design Engineer

Infoyogi LLC
Folsom

... -speed I/O circuits -Signal integrity (SI) & power integrity (PI) -Bump, RDL, package ... and power/grid layout creation Key Responsibilities ...

28 days ago

Silicon Design Engineer - Onsite

VIVA USA INC
Folsom

... , HSPICE, HFSS,signal integrity, SI, power integrity, PI,MATLAB, Python, modeling ... , perl, python,Bump, RDL, package, power layout creation, grid layout creation ...

29 days ago

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