Description: Verification Engineer Fremont, CA BSEE or BSCS, ... plansDesigning and implementing SystemVerilog / UVM test benches for constrained-random verificationDeveloping ... and debugging directed and random test casesExperience with automation/scripting ( ...
17 days ago
... : Software Engineer, Product: Develop, design, create, modify, and/or test software applications ...
22 days ago