Description: Role: Design Verification Engineer Location: Mountain View, CA (Hybrid) ... Type: Contract Job Description Design Verification Engineer Key Responsibilities: 08-14 Years ... Build UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
12 days ago
... for a highly skilled Physical Design Engineer to work at block level ... , timing closure, and sign-off verification. The role requires expertise in ...
14 hours ago