... Description: Overall Responsibilities: As a Packaging Design Engineer, you will create iconic, sustainable ... : Be responsible for the conception, design, development, documentation creation, validation and ...
13 hours ago
Description: Role: Design Verification Engineer Location: Mountain View, CA (Hybrid) ... Type: Contract Job Description Design Verification Engineer Key Responsibilities: 08-14 Years ...
5 days ago
... experience in PCIe Gen5 characterization 2. Engineer should be well versed in ... work with Synopsys, firmware, and design teame, in planning the testing ...
4 days ago
Description: PCIe Gen5 Validation Engineer Mountain View CA (Onsite) Contract 5+ ... experience in PCIe Gen5 characterization Engineer should be well versed in ... work with Synopsys, firmware, and design teams in planning the testing ...
5 days ago
Description: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Experience in complete verification cycle which includes development of ...
a day ago