Description: Role: RTL Integration Engineer Location: Sunnyvale CA (On-Site) ... experience in RTL design and integration (using Verilog, VHDL, or SystemVerilog ... digital design verification and subsystem integration. Experience with quality assurance tools ...
a day ago
Description: Job Title: Senior/ Lead ML Engineer Location: Mountain View, CA (4 Days ... position for a Senior Machine Learning Engineer with a strong background in Large ...
4 days ago
... main function of a Silicon Design Engineer is responsible of all design ... . These tasks include RTL design, integration, LINT, CDC, RDC, Synthesis. location ...
a day ago
... : As a Mid/Sr -level QA Engineer, you will be responsible for ... different devices and platforms.Independently lead QA efforts, drive quality of ...
4 days ago