... detailed requirement. Position : Physical Design Engineer (VLSI Design) Location : Mountain ... a highly skilled Physical Design Engineer with experience in Physical Design ... in Place and Route (P&R) and Static Timing Analysis (STA). Responsible for various ...
21 hours ago
... for a highly skilled Physical Design Engineer to work at block level ... , clock tree synthesis (CTS), routing, timing closure, and sign-off verification ...
13 hours ago
... with evaluation, annotation and data analysis for language/text tasks + Experience ...
2 days ago
... : 6 Months Job Title: Software QA Engineer (DHL) Mode of work: Onsite ... : As a Mid/Sr -level QA Engineer, you will be responsible for ... features including requirements and design analysis, test case creation & review and ...
20 hours ago
... : As a Mid/Sr -level QA Engineer, you will be responsible for ... features including requirements and design analysis, test case creation & review and ...
a day ago
Description: Job Role- Design Verification Engineer Location- Mountain View, CA (Onsite) ... and random testcases, perform coverage analysis, and close functional/code cover
4 days ago
... in Place and Route (PnR), Static Timing Analysis (STA), and Synthesis. The ideal ... , including floorplanning, clock tree synthesis, timing closure, and sign-off. This ...
19 hours ago