Description: Role: Design Verification Engineer Location: Mountain View, CA (Hybrid) ... : Contract Job Description Design Verification Engineer Key Responsibilities: 08-14 Years ...
26 days ago
Description: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI bus along-with ARM or C based processor Experience in complete verification cycle which includes development of ...
a day ago
Description: <> Key Responsibilities:Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog- ...
21 days ago