Description: Role: Design Verification Engineer Location: Mountain View, CA (Hybrid) ... Type: Contract Job Description Design Verification Engineer Key Responsibilities: 08-14 Years ... Build UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
a month ago
... C based processor Experience in complete verification cycle which includes development of ...
5 days ago
... requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
25 days ago