Description: job summary: Define, document, and implement a UVM verification environment including agents and scoreboards Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification ...
3 days ago
Description: job summary: 1. Experience with Synopsys Fusion Compiler (preferred) or Synopsys Design Compiler (ok) 2. Experience working as a CAD or AE engineer, supporting Front End Silicon Design tool flows (Synthesis, CDC, RDC, lint, etc.) 3. ...
9 days ago
Description: job summary: Analyze information to determine plan layout, including type of computers and peripheral equipment modifications. Power/PDN testing Assemble and modify existing pieces of equipment to meet special needs. Build, test, and modify ...
16 days ago
Description: job summary: Job Responsibilities: - Define, document, and implement a UVM verification environment including agents and scoreboards - Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, ...
25 days ago