Description: "Exciting Opportunity! We're seeking a Low Power Principal Engineer/ASIC Engineer to join our team in San Diego, CA! Key Responsibilities: - Low power design and verification (UPF, VCLP) - Power analysis and optimization (PTPX) - STA and ...
23 hours ago
Description: Pre-Layout Synthesis and STA Engineer Key Responsibilities: 1. Perform pre-layout synthesis to optimize digital designs for area, power, and timing. 2. Conduct static timing analysis (STA) to ensure design meets timing constraints. 3. Analyze ...
2 days ago