Description: Pre-Layout Synthesis and STA Engineer Key Responsibilities: 1. Perform pre-layout synthesis to optimize digital designs for area, power, and timing. 2. Conduct static timing analysis (STA) to ensure design meets timing constraints. 3. Analyze ...
a day ago
Description: Job Title: Senior Design Verification Engineer Company: Sivaltech Location: San Diego, CA Job Type: Full-time About Sivaltech: Sivaltech is a leading technology company driving innovation and excellence in the industry. We're seeking an ...
12 days ago
Description: About Us: Sivaltech is a leading VLSI service provider, delivering high-quality design and verification services to top semiconductor companies. We're seeking an experienced Senior Design Verification Engineer to join our team, supporting our ...
19 days ago