Description: Role: Design Verification Engineer Location: Bay Area, CA Hybrid ... : * Develop and implement verification plans for complex SoC designs, with a focus on ... using SystemVerilog and UVM (Universal Verification Methodology). * Write and execute test ...
18 days ago
Description: Job Title: Senior Physical Design Engineer (Full-Chip Expertise) Location: [ ... and execute full-chip physical design activities, including floorplanning, placement, ... signoff. Develop and implement physical design methodologies to achieve power, ...
18 days ago