... : Role: CAD/EDA Engineer Silicon Design/Verification Infrastructure Location: San Francisco, CA ... EDA/CAD SoC/IP design and/or verification infrastructure development. Proficiency in ... experience. Knowledge of ASIC/SoC design flows, SystemVerilog, and UVM. ...
13 days ago
Description: Should be good in hands-on using SV/UVM. AMBA (especially AXI is a must) Experience in updating sequence, test, running and debugging Experience in PCIE or C based is a plus
7 days ago
... for LLM-assisted RTL design, analysis, and verification.Work with RTL experts ... performance.Prompt Engineering and Optimization: Design, refine, and test
19 days ago