Description: Position-8: ASIC Design Verification Engineer Location: San Francisco Bay Area, ... skilled and motivated ASIC Design Verification Engineer with over 6 years of experience ... in the field of verification. As an Individual Contributor, he ...
5 days ago
Description: Senior Design Verification Engineer SV/UVM Contract Long Term ... francisco BayArea Key ResponsibilitiesOwn the verification of complex IP/subsystems using ...
23 days ago
Description: Static Timing Analysis (STA) Engineer <> Job Overview:We are seeking a ... Analysis (STA) Engineer to contribute to the timing verification and closure of ...
18 days ago