... experience High-speed layout design, High density PCB design, Cadence Allegro 16.x ... will Be Doing: Expert in PCB design tools Cadence Allegro 16.x ... experience in high density PCB design up to 28 layers ... high-speed layout design requirements Working knowledge
2 days ago
Description: Title: Verification Engineer Location: San Jose, CA (5 days ... the testbench architecture Strong in Design Functional Verification (SV/UVM) Software ...
17 days ago