Description: Job Title: Senior ASIC Design Engineer Location:San Jose ,CA Contract: 12+ MonthsWhat candidate will Be Doing: Technical: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip ...
7 days ago
Description: Job Title: Hardware Validation Engineer Location: San Mateo, CA (Complete onsite) Contract: 6+ Months Experience: 8+ YearsWhat candidate will Be Doing: We are seeking a driven and versatile engineer to help drive safety and reliability ...
8 days ago
Description: Job Title: PCB Layout Designer Location: Remote Contract: 6+ Months Experience: 7+ YearsNote: Team is seeking a Layout Designer with strong experience High-speed layout design, High density PCB design, Cadence Allegro 16.x &17.x,What ...
11 days ago
Description: Title: Verification Engineer Location: San Jose, CA (5 days onsite) Type: Contract Duration: 12+ Months Experience: 7+ years (Relevant)What candidate will Be Doing: Technical: Cadence Z2 (Palladium) and/or Synopsys HAPS-100 Emulation ...
26 days ago
Description: Job Role: Static Timing Analysis Engineer Location: San Jose, CA Type: Contract Duration: 12+ MonthsWhat will you do: Deliver on Static Timing Analysis domain with activities such as Timing Constraint Development/Modification, Running Chip ...
29 days ago