Description: Title: Verification Engineer Location: San Jose, CA (5 days ... )What candidate will Be Doing: Technical: Cadence Z2 (Palladium) and/or ... Design Functional Verification (SV/UVM) Software (Test) and Hardware (Emulation) ValidationWhat ...
22 days ago
... : Job Title: Senior ASIC Design Engineer Location:San Jose ,CA Contract ... + MonthsWhat candidate will Be Doing: Technical: Being a member of design team ...
3 days ago