... : Job Role: Static Timing Analysis Engineer Location: San Jose, CA Type ... , Running Chip level and Block level functional and Test level Static Timing Analysis ...
9 days ago
Description: Title: Verification Engineer Location: San Jose, CA (5 days ... ) Type: Contract Duration: 12+ Months Experience: 7+ years (Relevant)What candidate will ... for: At-least 2+ years of experience in emulation (Cadence Palldium, Synopys ...
5 days ago