Description: Position: PCIe Validation Engineer Exp: 5-8 years PCIe Gen 4/5/6, CXL, ... & Power Analyzer, BERTS C/C++, Python, Perl, Windows, Linux Take lead responsibility for ...
7 days ago
Description: Position: Hardware Design Engineer (Architect) Location: San Jose, USA ... , Power Integrity, Hardware design, Digital System Design, EDA tools, CAD Tools ...
3 days ago