Description: Position: Senior ASIC Design Engineer Emulation(HAPS Engineer) Location: San Jose, CA (Complete ... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ... engage in block-level RTL design or block or top-lev
13 days ago
Description: Position: Physical Design Engineer Location: San Jose CA (Day-1 ... Be Doing: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
22 hours ago