Description: Position: Senior ASIC Design Engineer Location: San Jose, CA (Complete ... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ... engage in block-level RTL design or block or top-level ...
3 days ago
... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ... engage in block-level RTL design or block or top-level ... IP integration.Collaborate with Software, Design, and Verification teams to validate ...
2 days ago