Description: PSV PCIE Validation & Emulation Engineer Experience: 5 to 8 years Salary Range ... and document PCIe validation test plans, test cases, and scripts. Perform ... interface. Collaborate with hardware/software design teams for successful integration ...
10 days ago
... Title: Power & Performance (PnP) Validation Engineer Location: San Jose, CA Company ... lab tools.Develop testbenches and test cases for RTL/firmware verification ...
10 days ago
Description: Job Title: SoC Lead Engineer Location: San Jose, CA Company: ... .Collaborate with verification teams for test planning and RTL simulation/debug ...
16 days ago
Description: PSV Memory Validation & Emulation Engineer Experience: 5 to 8 years Salary Range: ... system-level features. Apply hardware/software tools to ensure validation coverage ...
10 days ago