Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
5 days ago
Description: Signal Integrity EngineerIntroduction:An experienced Signal Integrity Engineer with at least 5 years of experience is needed to support high-speed interface development and validation. The engineer will be working on cutting-edge technologies ...
11 days ago