... Experienced (> 5y) Signal & Power Integrity Engineer to support high-speed interfaces ... into power delivery network (PDN) analysis. Responsibilities: All SI tasks ... above (channel modeling, extractions, eye analysis).Perform power integrity extractions and ...
8 days ago
... EngineerIntroduction:An experienced Signal Integrity Engineer with at least 5 years of ... interface development and validation. The engineer will be working on cutting ... channel modeling, extractions, and eye analysis for high-speed interfaces.Conduct ...
8 days ago
... a highly skilled and motivated DFT Engineer with 6+ years of experience to ... will have strong expertise in Design for Testability (DFT) methodologies, test ... . You will work closely with design, verification, and product engineering teams ...
8 days ago
Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
2 days ago