... : Experienced (> 5y) Signal & Power Integrity Engineer to support high-speed interfaces ... simulations for high-speed interfaces.Model and analyze package/board PDN ...
13 days ago
... a mixed signal chip (ADC), Digital based simulation environment, Test bench not ... need to develop models, Develop test plan etc.. System Verilog, Unix/Linux ... , Cadence tools Xcelium, Windows based tools.
7 days ago
... a mixed signal chip (ADC), Digital based simulation environment, Test bench not ... need to develop models, Develop test plan etc.. System Verilog, Unix/Linux ... , Cadence tools Xcelium, Windows based tools.
a day ago