Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
5 days ago
Description: Signal Integrity EngineerIntroduction:An experienced Signal Integrity Engineer with at least 5 years of experience is needed to support high-speed interface development and validation. The engineer will be working on cutting-edge technologies ...
11 days ago
Description: Signal & Power Integrity (SI/PI) EngineerRole: Experienced (> 5y) Signal & Power Integrity Engineer to support high-speed interfaces (LPDDR5X, PCIe Gen7, UCIe 64G), with responsibilities extending into power delivery network (PDN) analysis. ...
11 days ago
Description: Job SummaryWe are seeking a highly skilled and motivated DFT Engineer with 6+ years of experience to join our team in Santa Clara, CA. The ideal candidate will have strong expertise in Design for Testability (DFT) methodologies, test ...
11 days ago