Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
23 hours ago
... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
23 hours ago
... Technical Leadership: Lead hardwaresystems design projects guide design and architecture decisions that ... objectives.CrossFunctional Collaboration: Partner with Silicon Engineering, Data Center Operations, Cloud ...
23 hours ago
... : Technical Leadership: Lead hardwaresystems design projects guide design and architecture decisions that ... objectives.CrossFunctional Collaboration: Partner with Silicon Engineering, Data Center Operations, Cloud ...
23 hours ago
... design and verify features on LPU chips in simulation, emulation and silicon ... and methodologies for complex ASIC designs.Implement and optimize automated verification ...
18 hours ago