Description: Role: Hardware Systems Design Engineer Location: San Jose, CA (Onsite 3-4 ... ) AI/ML processors. Board-Level Design: Lead PCB layout and SI ... Bring-up: Design boards intended for ASIC bring-up and post-silicon
19 days ago
Description: Position: Hardware Systems Design Engineer Location: San Jose, CA (Onsite) ... -up: Design boards intended for ASIC bring-up and post-silicon validation ...
19 days ago
... design and verify features on LPU chips in simulation, emulation and silicon ... and methodologies for complex ASIC designs.Implement and optimize automated verification ...
14 days ago
... : Technical Leadership: Lead hardwaresystems design projects guide design and architecture decisions that ... objectives.CrossFunctional Collaboration: Partner with Silicon Engineering, Data Center Operations, Cloud ...
14 days ago
... chip and silicon IP provider is seeking a Principal Test Engineer to join ... high-performance products alongside top engineers and inventors, helping to make ... Test plan and work with design to ensure good Test coverage ...
12 days ago
... looking for Senior Validation Engineer for our client in ... CA Job Title: Senior Validation Engineer Job Location: San Jose, CA ... 68hr - $75hrIn this role, the engineer will be part of a highly ... -speed silicon interfaces such as DDR5 and LPDDR5. The engineer will ...
18 days ago
... chip and silicon IP provider is seeking a NPI Principal Product Engineer to ... of the brightest inventors and engineers in the world developing products ...
9 hours ago
... ? If so, Nutanix's CPU Enablement Engineer role might be an ideal ...
12 days ago
Description: Senior Software Engineer | Full-Time (Direct Hire) | Silicon Valley | Hybrid Work Schedule ...
17 days ago
Description: Sr. Solution Engineer - DevOps Software Solution Location: San ... #5 fastest growing company among the Silicon Valley Top 50 technology firms ...
18 days ago
Description: Sr. Solution Engineer - DevOps Software Solution Location: San ... #5 fastest growing company among the Silicon Valley Top 50 technology firms ...
18 days ago
Description: Package Design Engineer in the US, please share ... Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
20 days ago
... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
14 days ago
... resume along with LinkedIn Position : Package Designer Location: San Jose, CA ... creative and cost-effective IC package designs. Job Description:Netlist & BGA creationSubstrate ...
20 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
7 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
10 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
12 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
13 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
14 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
17 days ago