... Design Engineer - Senior Responsible for RTL design using Verilog HDL for implementation ... synthesis and backend teams for physical implementation. EDUCATION: Bachelor's or Master's in ...
15 days ago
Description: Title: Physical Design STA Engineer Location: San Jose, CA 95134 ... . STA Engineer with 15+ years experience for STA position (Physical Design Static ... Timing Analysis / STA Engineer).Perform static timing ...
22 days ago
... tests to fully test the implementations for new high-performance mass ...
10 days ago