... resume along with LinkedIn Position : Package Designer Location: San Jose, CA Duration ... experienced Packaging Designer to develop creative and cost-effective IC package designs. Job ...
6 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
a day ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
3 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
5 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
5 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
6 days ago
Description: Role: Hardware Systems Design Engineer Location: San Jose, CA ( ... ) AI/ML processors. Board-Level Design: Lead PCB layout and SI ... Bring-up: Design boards intended for ASIC bring-up and post-silicon
5 days ago
Description: Position: Hardware Systems Design Engineer Location: San Jose, CA ( ... -up: Design boards intended for ASIC bring-up and post-silicon validation ...
5 days ago
... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
a day ago
... : Technical Leadership: Lead hardwaresystems design projects guide design and architecture decisions that ... objectives.CrossFunctional Collaboration: Partner with Silicon Engineering, Data Center Operations, Cloud ...
a day ago
... design and verify features on LPU chips in simulation, emulation and silicon ... and methodologies for complex ASIC designs.Implement and optimize automated verification ...
19 hours ago