Description: Title: Static Timing Analysis Engineer Location: San Jose, CA Duration: ... a Static Timing Analysis Engineer with atleast 8 years of experience in Functional and test timing constraints, Static Timing Analysis ...
6 days ago
... Description: ASIC Package SI/PI Engineer Location: San Jose, CA 100 ... % Onsite ASIC Package Engineer SI/PI Responsibilities: Drive chip ... signal and power integrity requirements analysis and optimizationDefine power tree structure ...
5 days ago