$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key ... , Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good ...
28 days ago
Description: Title: Design Verification Engineer Location: San Jose, CA Duration: ... verilogtest cases for digital design verification.Perform FPGA designt
a day ago
... opening for Mixed-Signal Design Verification Engineer with our Client at San ...
8 days ago
Description: Role: Mixed-Signal Verification Engineer Location: San Jose, CA 100% ...
27 days ago
... and implement IP/SoC verification plans, build verification test benches to enable ... IP/sub-system/SoC level verification. Develop functional tests based on ... verification test plan. Drive Design Verification to closure based ...
28 days ago
Description: Job Title: Design Verification (DV) EngineerLocation: Bay Area, CAJob ... seeking a highly skilled Design Verification (DV) Engineer to join our team in ... background in Networking and SERDES verification. This role requires expertise in ...
27 days ago
Description: Title: Verification Test Engineer - Onsite Mandatory skills: software, firmware, ...
4 days ago