Description: Position: PCIe Validation Engineer Experience: 5 8 Years Location : San Jose , ... /5/6, CXL, RISC-V/ARM, Firmware, C/C++, Python, Lab Tools Role Highlights: PCIe subsystem ...
19 days ago
Description: Skill Need: PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, Multimeter, Logic & Power Analyzer, BERTS C/C++, Python, Perl, Windows, Linux Job Description Take lead responsibility for validating PCIe and its subsystems on multiple SoC ...
20 days ago