... an opening for Mixed-Signal Design Verification Engineer with our Client ... Good knowledge of System-Verilog RTL coding including state machines, adders ... , etc.Good understanding of digital design for mixed signal control loops ...
28 days ago
... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ... to engage in block-level RTL design or block or top-level ... IP integration. Collaborate with Software, Design, and V
17 days ago
... ) for complex chip-level ASIC designs Perform static timing analysis (STA ... with RTL, architecture, and physical design teams on clock structures and design intent ...
10 days ago
... timing constraints for complex ASIC designs at the chip level. Your ... cross-functional teams, including RTL designers, physical design engineers, and verification teams ...
10 days ago