Description: Position: Senior ASIC Design Engineer Emulation(HAPS Engineer) Location: San Jose, CA ( ... designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA ... in block-level RTL design or block or top- ...
4 days ago
... We are looking for a Senior Quality Assurance Engineer to join our team ... in agile environments. Key Responsibilities Design, develop, and execute detailed test ...
21 days ago
Description: Physical Design Engineer(Onsite) First preference : SAN JOSE, ... executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience ... in understanding and writing synthesis design constraints for hierarchical physical partitions ...
a day ago
Description: Physical Design Engineer Contract First preference : CA Second ... executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience ... in understanding and writing synthesis design constraints for hierarchical physical partitions ...
a day ago
$50
$60
an hour
... search for a Senior QA Engineer in Santa Clara, CA. Responsibilities: Design, develop, and ...
15 days ago
... a project team of engineers involved in the specification, design, development, and test ... engineer will work closely with hardware design engineers, software/diagnostic engineers, and manufacturing test engineers ...
8 days ago
... : Chip-Level Timing Constraint Development Engineer Location: San Jose, CA Onsite ... a Chip-Level Timing Constraint Development Engineer, you will be responsible for ... teams, including RTL designers, physical design engineers, and verification teams, to ensure ...
20 days ago
Description: Job Title: FPGA Engineer Location: San Jose, CA, USA ... Rate: DOE Key Responsibilities: Design and implement FPGA architectures using VHDL/Verilog ... translate requirements into specifications.Support FPGA integration, testing, and documentation. ...
2 days ago
... Description: Job Title: Hardware Engineer Location: San Jose, CA ... designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA ... in block-level RTL design or block or top ... Collaborate with Software, Design, and V
27 days ago
Description: Title: Design Verification Engineer Location: San Jose, CA Duration: ... experience with digital design, lab skills, and debugging in FPGA environments Nice ... System verilogtest cases for digital design verification.Perform FPGA designt
a month ago
Description: Job Title: SoC Lead Engineer Location: San Jose, CA Company: ... (ARM cores, SMMU, GIC) and design clock/reset architectures.Collaborate with ... , Lint/CDC checks, and support FPGA/emulation efforts.Key Skills: ARM ...
a day ago
... : Software Engineer (Frontend) San Jose, CA - onsite What You'll Do * Design ... product managers, business stakeholders, backend engineers, and users to translate requirements ... UI/UX best practices, proposing design improvements, and implementi
7 days ago
Description: Position: Sr. Hardware Engineer Location: Sanjose (Onsite) (Locals Need) ... concept to production Lead system design on embedded computing system products ... , Mechanical and SI engineers to complete the designs Bring up systems and ...
23 days ago
... from concept to productionLead system design on embedded computing system productsCreate ... with Layout, Mechanical and SI engineers to complete the designsBring up ...
a month ago
Description: Position: Senior Mobile Security Architect Location: San ... digital product engineering company that designs and develops chip-to-cloud ...
21 days ago
Description: Job Title: Senior Data Engineer (ERP, SQL, Python/PySpark, Google ... We are seeking a highly experienced Senior Data Engineer with over 8 years of ...
28 days ago
... digital product engineering company that designs and develops chip-to-cloud ...
22 days ago
Description: Job Title - Design Verification Engineer (GPU) Duration 6+ Months Location: San ... , CA Description As a GPU Design Verification Engineer, your talents will ensure the ...
2 days ago
Description: Job Title - Design Verification Engineer (GPU) Duration 9 + Month (With the ... w2 Description As a GPU Design Verification Engineer, your talents will ensure the ...
2 days ago
Description: Job Title:- ASIC Design Verification Engineer Duration:-12 months+ Location:-San ... a highly skilled and motivated ASIC Design Verification Engineer with over 6 years of ... of our cutting-edge ASIC designs, contributing to industry-leading ...
16 days ago
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