Description: Package Design Engineer in the US, ... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate ... assembly rule Possess Flip Chip Package Design Concept Good communication skill ...
10 days ago
... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate ... assembly rule Possess Flip Chip Package Design Concept Good communication skill ...
4 days ago
... , Cadence, PLA knowledge Multiple layers package design (8+) experienceUnderstanding of substrate manufacturing ... and assembly rulePossess Flip Chip Package Design ConceptGood communication skill.May ...
9 days ago