... Job Title: DFT / ATPG Engineer Job Location: Santa Clara, CA ... 82hr - $103hrThe DFT Design Engineer will be part of the ... role includes developing chip-level flows, pattern retargeting and ... simulations, and collaborating with test engineering teams for successful ...
24 days ago
... looking for Testbench/Verification Engineer for our client ... Job Title: Testbench/Verification Engineer Job Location: Santa Clara ... : $70hr - $86hrThe Verification Engineer will be responsible for developing ... at component or subsystem levels. This role requires ...
25 days ago