Where
Where

Jobs and careers for design engineer from the company Data capital inc in Santa Clara (16 jobs)

Sort by:
  • Data Capital Inc
  • Santa Clara
... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog ...
30 days ago
  • Data Capital Inc
  • Santa Clara
... experienced FPGA Verification Engineer to verify complex FPGA designs. You will develop ... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to ...
a month ago
  • Data Capital Inc
  • Santa Clara
... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog ...
28 days ago
  • Data Capital Inc
  • Santa Clara
... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog ...
30 days ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification ...
a day ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands-on experience with UVM (Universal Verification ...
3 days ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification ...
7 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
9 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
11 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
14 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
15 days ago
  • Data Capital Inc
  • Santa Clara
Description: Mandate Skills: FPGA ,System verilog coding,UVM 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification ...
16 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
17 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
23 days ago
Description: Job Discription: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, ...
28 days ago
Description: Job Discription: 3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, ...
29 days ago