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Jobs and careers for design verification engineer from the company Data capital inc in Santa Clara (16 jobs)

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  • Data Capital Inc
  • Santa Clara
... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay current ... verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design ...
28 days ago
  • Data Capital Inc
  • Santa Clara
... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay current ... verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design ...
30 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
18 hours ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
3 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
7 days ago
  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
8 days ago
  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
11 days ago
  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
14 days ago
  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
15 days ago
  • Data Capital Inc
  • Santa Clara
... UVM 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
16 days ago
  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
17 days ago
  • Data Capital Inc
  • Santa Clara
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
23 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys ...
28 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys ...
29 days ago
  • Data Capital Inc
  • Santa Clara
... an experienced FPGA Verification Engineer to verify complex FPGA designs. You will develop ... and execute verification plans, debug ... teams.Participate in design reviews and contribute to verification strategy.Stay curre
a month ago
  • Data Capital Inc
  • Santa Clara
... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay current ... verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design ...
30 days ago